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Creators/Authors contains: "Huang, Qicheng"

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  1. ; ; (, 2020 IEEE International Test Conference in Asia (ITC-Asia))
    null (Ed.)
    Logic diagnosis is a software-based methodology to identify the behavior and location of defects in failing integrated circuits, which is an essential step in yield learning. However, accurate diagnosis requires a sufficient amount of failing data, which is in contradiction to the requirement of reducing test time and cost. In this work, a dynamic test pattern reordering method is proposed to “recommend” which test patterns should be applied for a given failing chip, with the goal of maximizing failing data while minimizing test time. Unlike prior work that uses population statistics from already tested chips, this method uses a machine learning technique, namely k-Nearest Neighbors. Experiments using three industrial chips demonstrate the efficacy of the proposed methodology; specifically, the recommended test pattern order led to a 35% reduction, on average, while maximizing the amount of failure data collected. 
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  2. ; ; ; (, 2019 IEEE International Test Conference)
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  3. ; ; ; ; (, 2019 IEEE 37th International Conference on Computer Design (ICCD))
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